Why do I see recovery timing violations within the Altera POS-PHY Level 4 MegaCore in my design? - Why do I see recovery timing violations within the Altera POS-PHY Level 4 MegaCore in my design? Description Due to a problem with the auto generated synopsys design constraints (.sdc) file for the Altera® POS-PHY Level 4 (Receiver) MegaCore®, you may see recovery timing violations on paths from "*dpa_align:dpa_align|dpa_reset" to "*altlvds_rx_component|*auto_generated|rx*bit_slip_reg" . This is due to the following auto generated .sdc assignments being ignored: set_multicycle_path -setup -end -from "*dpa_align:dpa_align|dpa_reset" -to "*altlvds_rx_component|*auto_generated|rx[*]~bit_slip_reg" 2 set_multicycle_path -hold -end -from "*dpa_align:dpa_align|dpa_reset" -to "*altlvds_rx_component|*auto_generated|rx[*]~bit_slip_reg" 1 To workaround this problem, you can replace the assignments above (which can be found in the auto generated .sdc file) with the following assignments: set_multicycle_path -setup -end -from [get_keepers {*dpa_align:dpa_align|dpa_reset}] -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*~bit_slip_reg}] 2 set_multicycle_path -hold -end -from [get_keepers {*dpa_align:dpa_align|dpa_reset}] -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*~bit_slip_reg}] 1 This problem is scheduled to be resolved in a future release of the Altera Complete Design Suite. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Stratix® FPGAs', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']