Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to simulate when using the Synopsys* VCS*/VCS MX* simulator? - Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to simulate when using the Synopsys* VCS*/VCS MX* simulator? Description Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*, you may observe an error message saying the simulation stopped due to inactivity when using the Synopsys* VCS*/VCS MX* simulator. Resolution To work around this problem, when starting the simulation, execute the following command: sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log This problem is fixed in version 22.3 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15011371083 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']