AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions: Known Issues - AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions: Known Issues Description Issue 133244: Version 2.0 Table 2 shows all bits of the C counter, M counter, and N counter registers are Read/Write. The bypass enable (bit 16) and odd division (bit 17) bits of the C counter, M counter, and N counter registers of the Altera PLL Reconfig megafunction are write only. When any of these registers are read, bit 16 and bit 17 always return 0. Resolution This problem is fixed starting with AN661 version 13.1. Custom Fields values: ['novalue'] Troubleshooting 2205754738 False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']