IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG) - IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG) Hello everyone, I encountered an issue when assigning a simple GPIO to Bank M, where the HPS EMIF is connected. I would like to know whether it is possible to use I/Os on this bank while the HPS EMIF is enabled. Everything works as expected as long as the following pin assignment is not present: set_location_assignment PIN_P30 -to SE_IN[0] As soon as this assignment is added, the issue occurs, where SE_IN is an INPUT. Could you please let me know if using GPIOs on Bank M is supported when the HPS EMIF is configured? Regards, Andreas Replies: Re: IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG) Thanks, no more questions. Regards, Andreas Replies: Re: IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG) Thanks, glad to help. Do you have any further question, otherwise I will transition this thread to community support Thanks Regards Kian Replies: Re: IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG) Thanks a lot! That's exactly what I was looking for. Replies: Re: IO Placement issue when using HPS EMIF (1SX165HN3F43E2VG) Hi Andreas, There is some restriction on Stratix 10 IO banks with HPS EMIF due to hardwired connections. I would suggest to look at this guide here https://docs.altera.com/r/docs/683741/24.1/external-memory-interfaces-stratix-10-fpga-ip-user-guide/restrictions-on-i/o-bank-usage-for-stratix-10-emif-ip-with-hps Thanks Regards Kian