Why does the start_basic_test procedure fail when running the GTS JESD204B FPGA IP Design Example on the Agilex™ 5 FPGA hardware? - Why does the start_basic_test procedure fail when running the GTS JESD204B FPGA IP Design Example on the Agilex™ 5 FPGA hardware? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you may observe intermittent failures when running the start_basic_test procedure with the GTS JESD204B FPGA IP Design Example. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install the patch below. After installing the patch, do the following: Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤ RX Adaptation mode: Manual: if data rate <= 7Gbps Auto: if data rate > 7Gbps Regenerate the design example. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15018560395 novalue ['Interfaces JESD204B (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']