Stratix 10 HPS LED example - Stratix 10 HPS LED example Can someone suggest a basic HPS project with PIO for LED control. Need the complete flow of building the project from scratch. How to assign the HPS pins in Quartus. How to add uboot along with fpga pof file in QSPI flash. How to load linux in emmc. Replies: Re: Stratix 10 HPS LED example Hi Sajeev_antony, What you see Cold power-on → U-Boot → Linux starts → abrupt restart ~5 s into kernel (no panic text) Second boot succeeds to Linux; no further restarts until next power cycle SPL reports Reset state: Cold after the restart Two plausible cause: First-power-on reset race (FPGA/SDM/board timing) — fits “once per power-on, second try OK at same kernel point” Watchdog — U-Boot starts watchdog@ffd00200 (10 s); Linux must take over. On S10, WDT timeout can be configured as cold reset, so “Cold” does not rule WDT out. But ~5 s kernel time and identical second-pass timing make a simple 10 s timeout less convincing. How to prove it: After the spurious restart, at U-Boot: md.l 0xffd11000 1 (rstmgr status). Compare to intentional wdt expire. One trial: wdt stop before bootm. If double-boot disappears → WDT involved; if not → look at FPGA/SDM/cold reset path. Fix direction (after proof): If WDT: hand over to Linux (enable driver + service it), or stop in U-Boot only until Linux owns it — do not leave WDT off permanently. If FPGA/SDM: fix first-boot sequencing (config/bridges/nCONFIG/power) before HPS runs application software. refer: https://docs.altera.com/r/docs/683222/25.3.1/stratix-10-hard-processor-system-technical-reference-manual/signal-behavior-event-diagrams Replies: Re: Stratix 10 HPS LED example At power on boot of this HPS sytem we see a restart happening after these messages. This happens once every power on. after the restart it boost straight into the linux. Attached is the complete log of boot messages. What could be the issue. [ 5.041106] sdhci: Secure Digital Host Controller Interface driver [ 5.047287] sdhci: Copyright(c) Pierre Ossman [ 5.051777] Synopsys Designware Multimedia Card Interface Driver [ 5.058011] dw_mmc ff808000.mmc: IDMAC supports 32-bit address mode. [ 5.064613] sdhci-pltfm: SDHCI platform and OF driver helper [ 5.070312] dw_mmc ff808000.mmc: Using internal DMA controller. Replies: Re: Stratix 10 HPS LED example Hi, From the screenshot, it confirms that the FSBL is running successfully. However, the Secondary Stage Boot Loader (SSBL, i.e., bootloader.bin) still needs to be loaded, as USB functionality is only available in the SSBL stage. Trying to boot from MMC1 ** Partition 1 not valid on device 0 ** The log above indicates that the SSBL failed to load due to an invalid eMMC image. To proceed with SSBL bring-up, you can use either of the following methods: Debugger boot Follow this guide: https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/boot-examples/ug-linux-boot-s10-soc/#running-u-boot-with-the-debugger-from-command-line QSPI boot Refer to: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#boot-from-qspi Once the SSBL is up and running, you can: 1. Use fatload to load the USB image into RAM 2. Use mmc write to program the image from RAM into eMMC After programming the eMMC, you can reset the board to boot Linux from the eMMC. For generating a valid eMMC image, it is recommended to follow this guide: https://altera-fpga.github.io/rel-24.3/embedded-designs/stratix-10/sx/soc/emmc/ug-emmc-s10sx-soc/#build-flow Note: .itb is used for the bootloader (instead of .bin) Image is used for the kernel (instead of .bin) Additional required components include the .dtb and a root filesystem The steps to build all required binaries are detailed in the guide here: https://altera-fpga.github.io/rel-24.3/embedded-designs/stratix-10/sx/soc/emmc/ug-emmc-s10sx-soc/#build-flow If generating the eMMC image is not feasible, an alternative is to download it from: https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/sdimage.tar.gz You will need to decompress the archive before copying it to the USB drive. This image will create a valid partition layout on the eMMC. Afterward, you can replace the .itb and Image files using fatwrite. U-Boot does not support loading or executing raw .bin files directly. Example steps to create eMMC image: cd $TOP_FOLDER sudo rm -rf sd_card mkdir sd_card cd sd_card wget https://releases.rocketboards.org/2021.04/gsrd/tools/make_sdimage_p3.py chmod +x make_sdimage_p3.py # remove mkfs.fat parameter which has some issues on Ubuntu 22.04 sed -i 's/\"\-F 32\",//g' make_sdimage_p3.py mkdir fat && cd fat cp $TOP_FOLDER/u-boot-socfpga/u-boot.itb . cp $TOP_FOLDER/linux-socfpga/arch/arm64/boot/Image . cp $TOP_FOLDER/linux-socfpga/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb . cd .. mkdir rootfs && cd rootfs sudo tar xf $TOP_FOLDER/yocto/build/tmp/deploy/images/stratix10/core-image-minimal-stratix10.rootfs.tar.gz sudo rm -rf lib/modules/* cd .. sudo python3 ./make_sdimage_p3.py -f \ -P rootfs/*,num=2,format=ext3,size=64M \ -P fat/*,num=1,format=fat32,size=48M \ -s 128M \ -n emmc.img cd .. Replies: Re: Stratix 10 HPS LED example We are using Quartus 26.1 for all these activites. Replies: Re: Stratix 10 HPS LED example Our baord is a custom board with an 8GB eMMC. Option is provided to boot from JTAG and QSPI with MSEL switches. We could generate the .sof file by following the steps discussed earlier. We downloaded the precompiled first stage bootloader (FSBL) .hex as suggested earlier. Generated the .JIC file with the .sof and FSBL included in it and programmed the QSPI through JTAG. A FAT32 USB drive is plugged in to the USB port with second stage bootloader.bin and kernal.bin. Then we put MEL pins to boot from QSPI. Our expectation was that the HSP should boot with the linux in the USB drive. But we are getting this error message in the UART0 port. U-Boot SPL 2022.10 (Mar 20 2023 - 03:03:15 +0000) Reset state: Cold MPU 1200000 kHz L3 main 400000 kHz Main VCO 2400000 kHz Per VCO 2000000 kHz EOSC1 25000 kHz HPS MMC 20000 kHz UART 100000 kHz DDR: Warning: DRAM size from device tree mismatch with hardware. DDR: 4096 MiB QSPI: Reference clock at 400000 kHz WDT: Started watchdog@ffd00200 with servicing (10s timeout) denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000 denali-nand-dt nand@ffb90000: reset not completed. Trying to boot from MMC1 ** Partition 1 not valid on device 0 ** spl_register_fat_device: fat register err - -1 spl_load_image_fat: error reading image u-boot.itb, err - -1 Trying to boot from SPI SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Can you suggest what could be the issue. Also can you let us know the steps to install the linux in eMMC from the USB drive so that it can boot into linux from eMMC. Replies: Re: Stratix 10 HPS LED example Stratix® 10 devices use a Secure Device Manager (SDM) to control both FPGA configuration and HPS boot. As part of this architecture, .pof files are not used . Instead, the device is programmed using .rbf (Raw Binary File) images, which can includes the HPS bootloader. You may get the precompiled first stage bootloader (FSBL) .hex from here: https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/u-boot-spl-dtb.hex This bootloader is generated as part of the Yocto-based GSRD build flow. For more details on how it is built, refer to: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/ If you prefer to build the bootloader manually, you can follow this guide: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/boot-examples/ug-linux-boot-s10-soc/ The steps to include the bootloader into the .sof are documented here: https://docs.altera.com/r/docs/683847/26.1/stratix-10-soc-fpga-boot-user-guide/creating-the-configuration-files Example, if you have a HPS boot first design and configures via JTAG: quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on For QSPI boot, you can follow this guide: https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#boot-from-qspi A detailed description of the boot flow is available here: https://docs.altera.com/r/docs/683847/26.1/stratix-10-soc-fpga-boot-user-guide/boot-flow-overview At a high level: 1. SDM reads the configuration image (e.g., from QSPI, SD, EMMC, or JTAG) 2. SDM loads the FSBL into HPS on-chip RAM 3. HPS starts executing the FSBL 4. FSBL initializes DDR and loads the next-stage bootloader (SSBL / U-Boot) For SDM-based devices: No additional RAM for the HPS needs to be added in the FPGA fabric Once the RBF is loaded, the FSBL runs from HPS OCRAM, and the rest of the boot sequence proceeds from there. Replies: Re: Stratix 10 HPS LED example Thank you for the details. Now iam able to compile the desigsn and the .sof is getting generated. Now need to add the bootlaoder .hex fille to generate the .pof programming file. Can you let me know from where can i get the boot loader file and the steps to add it to the FPGA programming file. From where does the boot loader run? From QSPI flash or do we need to create an internal RAM in FPGA for the HPS? Replies: Re: Stratix 10 HPS LED example thank you for the report. Based on the report, you can search for “I/O Assignment Warnings”, which should provide relevant details. A sample snippet is shown below for reference. +-----------------------------------------------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +--------------------------+--------------------------------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +--------------------------+--------------------------------------------------------------------------------------------------------------------+ ; hps_usb_uart_tx ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; hps_spim0_CLK ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; hps_spim0_MOSI ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; hps_spim0_SS0_N ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; hps_spim0_SS1_N ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; hps_usb1_STP ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; hps_sdmmc_clk ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin ; ; fan1_pwm ; Missing drive strength and slew rate on output pin, a default slew rate value of 1 has been used ; ; fan2_pwm ; Missing drive strength and slew rate on output pin, a default slew rate value of 1 has been used ; You may refer to the following guide for configuring the I/O standard: https://docs.altera.com/r/docs/683518/24.3/stratix-10-general-purpose-i/o-user-guide/stratix-10-i/o-overview From the report, I also noticed that the fitter has assigned the EMIF pins (example shown above). However, I would recommend cross-checking these assignments against your board schematic to ensure correctness. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Output Pins ; +--------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-------------------------+------------------+-----------------------------------+---------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; +--------------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+------------+---------------+----------+--------------+-------------------------+------------------+-----------------------------------+---------------------------------------------------------------------------------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ ; board_leds[0] ; A39 ; 2K ; 61 ; 156 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ; board_leds[1] ; B36 ; 2K ; 61 ; 155 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ; board_leds[2] ; B37 ; 2K ; 61 ; 154 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ; board_leds[3] ; B39 ; 2K ; 61 ; 153 ; 61 ; no ; no ; 1 ; no ; no ; no ; Off ; 1.8-V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ; ddr4_emif_mem_a[0] ; F28 ; 2M ; 61 ; 220 ; 31 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ; ; ddr4_emif_mem_a[10] ; A29 ; 2M ; 61 ; 230 ; 31 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ; ; ddr4_emif_mem_a[11] ; A28 ; 2M ; 61 ; 231 ; 31 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ; ; ddr4_emif_mem_a[12] ; B26 ; 2M ; 61 ; 223 ; 46 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ; ; ddr4_emif_mem_a[13] ; B27 ; 2M ; 61 ; 224 ; 46 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ; ; ddr4_emif_mem_a[14] ; A27 ; 2M ; 61 ; 225 ; 46 ; no ; no ; 1 ; no ; yes ; no ; Off ; SSTL-12 ; Default ; Series 34 Ohm with Calibration ; u0|emif_s10_hps_0|emif_s10_hps_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst ; 1 ; no ; Fitter ; - ; - ; You can find the 26.1 Quartus project at the following link: s10_soc_htile_devkit_emmc_QPDS-26.1pro.zip https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/ This is the same .zip package that I previously attached. To regenerate the project, you can follow the steps here: git clone https://github.com/altera-fpga/stratix10-ed-gsrd.git cd stratix10-ed-gsrd git checkout QPDS26.1_REL_GSRD_PR make s10-htile-soc-devkit-emmc-baseline-generate-design cd s10_soc_devkit_ghrd After that, you can open the Quartus project: ghrd_1sx280hu2f50e1vgas.qpf May i know if you are using stratix-10-sx-soc-development-kit or a custom board? Replies: Re: Stratix 10 HPS LED example You may kindly refer this latest fitter report file from Quartus 26.1 Replies: Re: Stratix 10 HPS LED example Fitter report attached. Also can you help me to get started with the GSRD. How to generate the Quartus project from the GSRD. Coun't find any Quartus project file in it. Replies: Re: Stratix 10 HPS LED example Regarding the attachment, I have rechecked it. Please kindly rename the .rpt file to .txt before uploading. I can attach a zip file. Replies: Re: Stratix 10 HPS LED example thank you for the feedback. You are right, i cant add any attachment too. I will feedback that to the team. I recommend comparing your .qsf file against the version provided in the zip file here: https://releases.rocketboards.org/2026.04/emmc/s10_htile_emmc/s10_soc_htile_devkit_emmc_QPDS-26.1pro.zip For the DDR4 pins, the user may also need to manually assign the corresponding pins in the .qsf file. If you are using both HPS and EMIF, I recommend starting from the example here as a baseline: https://github.com/altera-fpga/stratix10-ed-gsrd Replies: Re: Stratix 10 HPS LED example How to upload report files. it dosnot allow me to upload the file. Iam using HPS and hard EMI for DDR4. Do i have to assign pin for DRR4 or will the quatrus auto assigne it. Replies: Re: Stratix 10 HPS LED example Hi Sajeev_antony, There is a QSF setting that promotes specific warnings to errors. # Promote pins without location assignments to errors set_global_assignment -name PROMOTE_WARNING_TO_ERROR 12677 If this option is enabled, all top-level pins are required to have complete assignments, including: Location I/O standard For a quick initial test, I would suggest disabling this setting to allow the build to proceed without being blocked by these checks. If you would like to identify the exact pin(s) causing the issue, could you please share the full fitter report? Thank you. Best regards, shun jing. Replies: Re: Stratix 10 HPS LED example On compiling the Quartus project with Stratix 10 HPS, iam getting this warning and the programming file is not getting generated. Critical Warning(25196): A programming file will not be generated because the assembler identified user pins missing pin location assignments. Refer to the I/O Assignment Warnings table in the fitter report for a list of unassigned pins. You can assign these pins in the Pin Planner tool and recompile to allow programming file generation to pass. Critical Warning(25207): A programming file will not be generated because the assembler identified some pins have missing I/O Standard assignments. Refer to the I/O Assignment Warnings table in the fitter report for details. But in the fillter report there are no unassigned pins. Any idea what could be the issue. Replies: Re: Stratix 10 HPS LED example Thank you for teh explanation. Replies: Re: Stratix 10 HPS LED example They got assigned based on the PINMUX selection where the user selects the peripherals to be enabled. Quartus will automatically, picked the IOs and assigned them respectively. As per the spec (if i am not mistaken), you can't assign HPS dedicated pin locations in pin planner because the package balls are fixed per device. You can only choose the function and mux as i explained above in the HPS Platform designer. Pin planner is basically for reviews only. Then, it will be translated to a handoff (part of the bitstream) for the HPS FSBL to then configure the PINMUX/IO manager. If you are looking for the GPIO for LEDs, they are as followed below. If you are using the GHRD official design, you can then, control the LEDs output through this IOs. Replies: Re: Stratix 10 HPS LED example After selecting the HPS peripheral in the auto place IP, the HPS pins come up in the top level instantiation. These HPS pins eg. SDMMC, USB etc which are part of HPS show up in the FPGA pin planner. But not able to assigne any location to it. How do the locations get assigned to these dedicated HPS pins. Replies: Re: Stratix 10 HPS LED example Hi Sajeev_antony, Please refer to the following resources: https://docs.altera.com/r/docs/683516/22.4/stratix-10-hard-processor-system-component-reference-manual/auto-place-ip https://altera-fpga.github.io/rel-26.1/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/ https://altera-fpga.github.io/rel-24.3/embedded-designs/stratix-10/sx/soc/emmc/ug-emmc-s10sx-soc/ I hope that helps. Sue