Why does my FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* show lower read performance in Quartus® Prime Pro version 19.3? - Why does my FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* show lower read performance in Quartus® Prime Pro version 19.3? Description The FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* currently supports up to 64 outstanding requests with a Max Read request size of 512 Bytes. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput. Resolution Tune BIOS settings for performance to reduce latency. Custom Fields values: ['novalue'] Troubleshooting 14010045894 False ['Avalon-MM Stratix® 10 Hard IP+ for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.3 ['Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']