How can I cause toggling "dlup_exit" interface signal of PCIe to verify external user logic connecting to the "dlup_exit" in simulation ? - How can I cause toggling "dlup_exit" interface signal of PCIe to verify external user logic connecting to the "dlup_exit" in simulation ? Description The "dlup_exit" interface signal of PCIe® core indicates that "Data Link Control and Management State Machine" exists Data Link Up state. To cause toggling the "dlup_exit" in simulation, force rxdata0_ext (in PIPE mode) or rx_in0-7 (in non PIPE mode) signals to Zero(0) during link-up (LTSSM=0x0F). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']