XAUI PHY FPGA IP - The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… The XAUI PHY FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Defense Government Industrial Transportation Wireless XAUI PHY FPGA IP Key Features Complete 10G Ethernet (XAUI) PHY solution for 4X 3.125 Gbps serial external interface Offering Brief No No No No Encrypted Verilog No Yes Offering Brief Production a1JUi0000049UUcMAM What's Included Encrypted Verilog source code Ordering Information IP-XAUIPCS Mouser a1JUi0000049UUcMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T16:52:16.000+0000 The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP. Altera Solutions