Error (170152): Initial placement of LogicLock Plus hierarchy failed after <N> attempts. - Error (170152): Initial placement of LogicLock Plus hierarchy failed after <N> attempts. Description Automatic periphery placement of design logic that has LogicLock ™ or LogicLock Plus constraints might generate a clock placement that requires more core resources in a clock region than are available, causing initial placement to fail with an error message similar to the following: Error (170152): Initial placement of LogicLock Plus hierarchy failed after 2 attempts. LogicLock Plus region "|" had the largest number of placement failures, but may or may not be the cause of the problem. You may be able to correct the situation and achieve placement, by manually altering one or more LogicLock Plus regions This issue affects the Quartus ® II software, the Quartus Prime Standard Edition software, and the Quartus Prime Pro Edition software. Resolution Manually specify alternative clock region constraints for any logic that cannot fit because it requires too many resources. When specifying alternative clock region constraints, the following options are available: Use the GLOBAL_SIGNAL assignment to specify a clock type that is larger in size. Use the CLOCK_REGION assignment to specify an alternative clock region. Use location constraints to select an alternative clock buffer placement. Custom Fields values: ['novalue'] Troubleshooting FB366973; True ['Basic Functions Clocks (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 16.1 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']