Why does the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example generation fail? - Why does the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example generation fail? Description Due to a problem in the Intel® Quartus® Prime Pro Edition version 21.2 Software, you may see the Triple-Speed Ethernet Intel® FPGA IP 10/100/1000Mb Ethernet MAC (Fifoless) with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver Design Example generation fail. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.2. Download and install Patch 0.15 from the appropriate link below. Download the patch Intel® Quartus® Prime Pro Edition version 21.2 Patch 0.15 for Windows (.exe) Download the patch Intel® Quartus® Prime Pro Edition version 21.2 Patch 0.15 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition version 21.2 Patch 0.15 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 1509349576 True ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']