Error May Occur When Simulating VHDL Designs With MMR Enabled Using VCS-MX - Error May Occur When Simulating VHDL Designs With MMR Enabled Using VCS-MX
Description A segmentation fault may occur when simulating an Arria 10 EMIF IP in VHDL with MMR enabled, using Synopsys VCS-MX. Resolution The workaround for this issue is as follows: Run vhdlan without the -xlrm option. Run vcs with the -xlrm option. This problem will be fixed in a future version.
Custom Fields values:
['novalue']
Troubleshooting
FB328762;
True
['novalue']
['FPGA Dev Tools Quartus® Prime Software Pro']
16.1
15.1
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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