Why does simulation of the Intel® Stratix® 10 FPGA JESD204B IP design example fail when using the ModelSim SE version 10.5c? - Why does simulation of the Intel® Stratix® 10 FPGA JESD204B IP design example fail when using the ModelSim SE version 10.5c?
Description Simulation of the Intel® Stratix® 10 JESD204B design example generated in the Intel® Quartus® Prime Software version 17.1.1 or earlier might fail when simulating at a resolution of 1 ps usng the ModelSim SE version 10.5c. Resolution To work around this problem, remove the 1 ps resolution from the vsim command line by removing '-t ps' from the vsim command in the modelsim do file msim_setup.tcl. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.
Custom Fields values:
['novalue']
Troubleshooting
FB: 500510;
False
['JESD204B IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
18.1
17.0
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-09
external_document