L/H-Tile PCIe* Hard IP - L/H-Tile are each an FPGA companion tile that supports PCI Express* configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes. Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA L/H-Tile are each an FPGA companion tile in Stratix® 10 FPGA devices that support configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes. Additionally, H-Tile includes support for SR-IOV functionality. PCI Express (IP) Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Wireless L/H-Tile PCIe* Hard IP Key Features Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with up to PCIe 3.0 lane rates. Offering Brief Yes No No Yes Encrypted Verilog Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Yes Yes Offering Brief Production a1JUi000004N4tRMAS What's Included Encrypted Verilog Source Code Ordering Information No license required Direct a1JUi000004N4tRMAS Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-10-24T17:24:16.000+0000 L/H-Tile are each an FPGA companion tile that supports PCI Express* configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes. Altera Solutions