Using the GTS PCIe* Hard IP - 33 Minutes Agilex™ 5 and Agilex™ 3 FPGAs with GTS transceivers provide a flexible solution for designs requiring Gen3 and Gen4 PCI Express* connections. The Using the GTS Transceiver PCI Express Hard IP course can help you get started in using the PCIe* hard IP for your design. After reviewing the GTS transceiver architecture, this course will walk you through the transceiver block when configured for PCI Express interfaces. It will then introduce you to the IP that you will need to complete your design. Finally, the course will provide some important guidelines regarding the PCIe hard IP that will help with your design’s success. This course will also compare the GTS transceiver PCIe hard IP with older Altera® FPGA families, for those migrating from older architectures. Course Objectives At course completion, you will be able to: Customize the GTS transceiver PCI Express Hard IP Build an FPGA design using GTS transceiver PCI Express Hard IP Skills Required Understanding of the PCI Express specification Familiarity with FPGA/CPLD design flow Familiarity with the Quartus® Prime Pro design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OGTSPCIE. FPGA_OGTSPCIE. <p>Using the GTS PCIe* Hard IP</p>