Why does the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example simulation fail when using the Questa*-Altera® FPGA Edition Software? - Why does the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example simulation fail when using the Questa*-Altera® FPGA Edition Software? Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and later, simulation of the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example with PIPE mode enabled will fail when using the Questa*-Altera® FPGA Edition Software. Refer to the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example User Guide Version Found: 25.1 Resolution To work around this issue, do one of the following: Generate the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example with PIPE Mode Disabled when simulating with the Questa*-Altera® FPGA Edition Software or, Use full version of the Questasim* Software to simulate the R-Tile Avalon® Streaming FPGA IP for PCI Express* Design Example with PIPE Mode enabled. A patch is NOT available to fix this issue This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 14025850518 novalue ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']