Why does the transceiver pll_locked signal deassert when rx_analogreset is asserted during simulation of Cyclone® IV GX devices? - Why does the transceiver pll_locked signal deassert when rx_analogreset is asserted during simulation of Cyclone® IV GX devices? Description The transceiver pll_locked signal deasserts when rx_analogreset is asserted during simulation of Cyclone® IV GX devices due to an incorrect simulation model. The transceiver rx_analogreset signal incorrectly resets the MPLL and causes the pll_locked signal to deassert in the Quartus® II software version 9.1-SP2. The following patches are available to fix this problem: Quartus II Software version 9.1-SP2 Patch 2.38 for Windows Quartus II Software version 9.1-SP2 Patch 2.38 for Linux Quartus II Software version 9.1-SP2 Patch 2.38 Readme file This problem is fixed in the Intel® Quartus® Prime Software v16.0. Resolution This issue is fixed in Quartus Prime Software 16.0. Custom Fields values: ['novalue'] Troubleshooting 2205867084 False ['novalue'] ['novalue'] novalue novalue ['Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']