Why does the Mailbox Client Intel® FPGA IP not function correctly when connected to an asynchronous reset? - Why does the Mailbox Client Intel® FPGA IP not function correctly when connected to an asynchronous reset? Description In Intel® Quartus® Prime Pro Edition software versions 19.4 and earlier, you may find that the Mailbox Client Intel FPGA IP does not function correctly when connected to an asynchronous reset including the output of the Reset Release Intel® FPGA IP when using Intel® Stratix® 10 devices. Resolution To work around this, a reset synchronizer should be used with the Mailbox Client Intel FPGA IP . This can be implemented using the Reset Bridge IP available in Platform Designer. This problem is fixed starting with Intel Quartus Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1808745414 False ['Mailbox Client Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']