Does Intel provide support for Multi-port Front End IP implemented in the core FPGA fabric? - Does Intel provide support for Multi-port Front End IP implemented in the core FPGA fabric? Description Multi-port Front End logic can be used to connect multiple Avalon® bus masters to a single port Avalon slave memory controller. Currently Altera does not provide support for soft Multi-Port Front End IP with identical functionality to the hard Multi-Port Front End IP implemented in Arria® V and Cyclone® V devices. However, these sources of information may be useful as a starting point for users who require Multi-Port Front End functionality in the FPGA core logic : Application Notes AN637: Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design (PDF) Design files for AN 637 Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV FPGAs', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']