Why does the EMIF Traffic Generator 2.0 incorrectly assert the fail signal? - Why does the EMIF Traffic Generator 2.0 incorrectly assert the fail signal? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, you may see the EMIF Traffic Generator 2.0 (TG2) incorrectly assert the fail signal when the TG2 is configured such that TG_USER_WORM_EN = 1, TG_RETURN_TO_START_ADDR = 1, TG_ADDR_MODE = random or random-sequential, and TG_WRITE/READ_REPEAT_COUNT > 1. This problem occurs because the random address generator does not wait for the read/write repeats to finish on the last iteration of the loop before resetting the address, which causes an incorrect comparison in TG2. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 14012501674 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']