Verilog HDL Simulation Fails - Verilog HDL Simulation Fails Description Running a simulation with the Verilog HDL testbench results in an empty summary_output.txt file. This issue affects all Verilog HDL configurations. You cannot use the summary_output.txt file to evaluate the functionality of the design. But you can evaluate the functionality by looking at the simulation waveform. Resolution Run the simulation with a VHDL design and use the VHDL testbench. This issue will be fixed in a future release of the Reed-Solomon Compiler. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']