Why might my Stratix V PCI Express Gen1/2 link fail to train correctly? - Why might my Stratix V PCI Express Gen1/2 link fail to train correctly? Description Due to non-optimal PMA settings for Gen1 and Gen2 designs in the Stratix® V PCI Express® Hard IP core, you may experience a problem with your PCI Express link failing to correctly train to the L0 state, and instead may observe that the LTSSM toggles between 0,1,2,4,0,1,2,4.... Resolution This problem has been fixed in Quartus® II software version 12.0 DP2 and later. Refer to the following link for instructions to install the Device Patch (DP): http://www.altera.com/support/kdb/solutions/rd06202012_726.html Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']