Possible Timing Failures for LPDDR2 Designs on Cyclone V -7 Speed Grade Devices - Possible Timing Failures for LPDDR2 Designs on Cyclone V -7 Speed Grade Devices Description This problem affects LPDDR2 products. LPDDR2 designs targeting Cyclone V -7 speed grade devices at 333 MHz may fail address and command timing analysis. Resolution The workaround for this issue is to operate the design at a lower frequency (such as 300 MHz), or use a -6 speed grade Cyclone V device. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 12.1.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']