HDL-03 - Introduction to Verilog - 2 Days - Enroll Now This course provides a practical, hands-on foundation in using Verilog HDL for digital design. Participants will learn how to model, simulate, and verify hardware designs while developing a thorough understanding of synthesizable coding practices. The course combines instructor led discussion with guided labs using Altera Quartus® Prime and ModelSim to reinforce key concepts and build real world design confidence. By the end of the course, participants will be able to write, simulate, synthesize, and implement Verilog designs targeting Altera FPGAs. Emphasis is placed on professional coding style, design reuse, and the development of verification skills that scale from simple unit tests to system level integration Course Content: 1. Overview & FPGA Design Flow 2. Introduction to Verilog HDL 3. Language Fundamentals — Data Types, Operators & Expressions 4. Module Structure & Port Declarations 5. Dataflow & Gate Level Modelling 6. Behavioural Modelling — always Blocks & Procedural Assignments 7. Registers, Flip Flops & Latches 8. Counters & Shift Registers 9. Finite State Machines (Mealy & Moore) 10. Testbench Design Fundamentals 11. Parameters, localparams & Generate Statements 12. Module Instantiation & Hierarchy 13. Synthesis Guidelines & Synthesizable Coding Practices 14. Quartus Compilation, Fitter & Timing Analysis 15. FPGA Architecture Deep Dive (LEs, DSPs, PLLs) 16. Memory Modelling — ROMs, RAMs & FIFOs 17. Altera IP Catalog & Megafunctions 18. Platform Designer Integration 19. Advanced Verilog — Tasks, Functions & System Tasks 20. Verilog for Verification & Bus Functional Models 21. FPGA Design Patterns & CDC Techniques 22. Design-for-Test & In-System Debugging (SignalTap) 23. Synthesis Optimization & Resource Management 24. Production Design Practices & Code Review 25. Course Review, Q&A & Next Steps Prerequisites: - Familiarity with digital logic concepts (combinational and sequential circuits, Boolean algebra) - Basic understanding of computer architecture (registers, buses, memory mapped I/O) - Experience with at least one programming language (C, C++, Python, or similar) Recommended - Prior exposure to an HDL (VHDL or Verilog) at an introductory level - Experience with a command line environment (Linux terminal or Windows PowerShell/Git Bash) - Familiarity with FPGA concepts (LUTs, flip flops, I/O banks) is helpful but not required Tools Required: - Quartus® Prime Software - ModelSim-Altera® FPGA Starter Edition (Questa) - SignalTap Logic Analyzer - Visual Studio Code Course code: HDL 03. FA_VERILOG.