Low-Density Parity-Check (LDPC) Codes Altera® FPGA IP for 5G Systems - 18 Minutes As wireless vendors begin to deploy 5G-based technology, Low-Density Parity-Check (LDPC) codes are replacing turbo codes as the coding of choice for forward error correction. This training introduces the Altera® FPGA LDPC Codes IP cores, namely the encoder and decoder blocks . It shows the basics of how these blocks work and then describes how, when using the cores, you can verify correct operation in both the simulation and hardware environments using a core-generated reference design. Course Objectives At course completion, you will be able to: Understand the basic function of the 5G LDPC codes IP core Verify the functionality of the 5G LDPC codes IP core in simulation Verify the functionality of the 5G LDPC codes IP core in hardware using the Signal Tap logic analyzer Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime Pro design software knowledge of Forward error correction algorithms, particularly low-density partity-Check codes If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_O5GLDPC. FPGA_O5GLDPC. <p>Low-Density Parity-Check (LDPC) Codes Altera FPGA IP for 5G Systems</p>