SPMI-CTRL: MIPI SPMI Controller or Target - The SPMI-CTRL IP core implements the MIPI System Power Management Interface (SPMI) v2.0 protocol, enabling efficient and standardized communication between power management ICs (PMICs) and other… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either controller or target nodes in an SPMI bus. The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check address and data parity. CAST is a MIPI Alliance member Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host, which can be used for a higher application layer or for debugging purposes. Last received command, outgoing command status, bus status, and node operation status are made available to the host via the core’s registers. Parity errors, unknown commands, or failure of receiving node to provide ACK/NACK response are also reported. Furthermore, the core can be programmed to operate in debug mode, under which the core captures and reports all SPMI bus commands regardless of the destination address. Integration of the core is extremely simple: The core provides access to its registers via a AMBA™ 2 APB target interface, and converts the incoming SPMI read/write commands to accesses on its AHB controller port. This SPMI-AHB bridging allows easy mapping of the SPMI address space to shared memories or peripheral registers. A dedicated interface allows integration with application specific authentication logic, which can be reduced to just hardwiring the authentication response data. The core uses separate clocks for its APB and AHB bus interfaces, and a separate reference clock source for its internal timer. Clocks are independent to each other, with clean clock domain crossing boundaries, and the only requirement is that the AMBA interface clocks have a frequency larger or equal to the maximum SPMI clock frequency. The core is designed with industry best practices, and its reliability has been proven through rigorous verification. Audio / Video Access Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Test Wireless SPMI-CTRL: MIPI SPMI Controller or Target Key Features Supports High Speed (HS) and Low Speed (LS) device classes Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U70MAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information SPMI-CTRL a1JUi0000049U70MAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-10-31T21:34:56.000+0000 The SPMI-CTRL IP core implements the MIPI System Power Management Interface (SPMI) v2.0 protocol, enabling efficient and standardized communication between power management ICs (PMICs) and other components in complex SoCs. It can operate as either a controller or a target, making it flexible for a wide range of designs. The core autonomously manages critical protocol tasks such as command execution, ACK/NACK responses, arbitration, and address/data parity, minimizing host processor involvement and reducing system overhead. Its architecture is optimized for reliability and interoperability, ensuring robust power control and communication in mobile, automotive, and IoT devices. Supporting both single-master and multi-master configurations, the SPMI-CTRL offers scalability to meet diverse system requirements. Easy integration with standard system buses and configurability make it a practical, high-performance solution for developers implementing advanced power management networks. Partner Solutions