Why is flashsm_reset reported as an unconstrained clock in the PFL IP? - Why is flashsm_reset reported as an unconstrained clock in the PFL IP? Description Due to a limitation in the Intel® Quartus® Prime software, you may see flashsm_reset reported as an unconstrained clock. This occurs when you instantiate the Parallel Flash Loader (PFL) IP in an Intel® MAX® 10 device. Resolution flashsm_reset is not a clock, so it is safe to ignore this warning. Custom Fields values: ['novalue'] Troubleshooting 1506795151 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 16.0 ['MAX® 10 10 FPGAs'] ['MicroBlaster™ Fast Passive Parallel Software Driver'] ['novalue'] ['novalue']