Why do simulated Avalon® Memory Mapped transactions take up to 16us to complete on the GTS PMA/FEC Direct PHY FPGA IP for the Agilex™ 5 FPGA devices when using the Quartus® Prime Pro Edition Software version 24.1? - Why do simulated Avalon® Memory Mapped transactions take up to 16us to complete on the GTS PMA/FEC Direct PHY FPGA IP for the Agilex™ 5 FPGA devices when using the Quartus® Prime Pro Edition Software version 24.1? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, simulated Avalon® Memory Mapped transactions may take up to 16us to complete on the GTS PMA/FEC Direct PHY FPGA IP for Agilex™ 5 devices. Agilex™ 5 silicon does not exhibit this problem. Resolution There is no plan to fix this problem in the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16023592203 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']