Why do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface? - Why do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you will see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16 bit PMA interface and placed in 200G Hard IP. The Quartus Logic Generation Error message might be similar to one of the followings: Error(22144) Error(22658) Error(21843) Resolution There is no plan to fix this problem. To work around this error, you can take one of the below two methods: Change the clocking mode from PMA clocking mode to System PLL clocking mode, or Change the F-Tile placement from 200G Hard IP to 400G Hard IP. Custom Fields values: ['novalue'] Troubleshooting 16025079224 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGA Direct RF-Series', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']