Hardware Design Flow for Altera® SoC FPGAs - Same Course in Simplified Chinese: 基于ARM的芯片系统硬件设计流程 Same Course in Japanese: ARMベースSoC向けハードウェア・デザイン・フロー 50 Minutes This course is intended for hardware and firmware engineers, it examines the hardware design flow required to implement an Altera® SoC FPGA with the Arm*-based Hard Processor System as an FPGA Component IP inside Platform Designer. This course discusses the tools and methodology necessary to design and verify your system. You will gain an understanding of exactly what’s required to implement a system using Altera® SoC FPGAs. Course Objectives At course completion, you will be able to: Create an Altera® SoC FPGA system using the Quartus® Prime software and Platform Designer system integration tool Understand the necessary steps to create a custom component that interacts with the HPS as an FPGA Component IP Debug using the System Console tool Understand features included in Altera® FPGA development tools to perform FPGA-adaptive software debug Skills Required FPGA knowledge is not required, but a plus If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OSOC1000. FPGA_OSOC1000. <p>Hardware Design Flow for Altera SoC FPGAs</p>