Qsys incorrectly reports the clock rate of an IP core as 0 MHz - Qsys incorrectly reports the clock rate of an IP core as 0 MHz
Description In the Quartus II software release version 14.1, Qsys may incorrectly report the clock rate of an IP core as 0 MHz. This issue may occur in Altera IP cores or IP cores you define in _hw.tcl using composition for use in Qsys. Resolution There is no workaround.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
14.1.1
14.1
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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