Why does the Configuration Clock IP generate an SDC file with incorrect constraints for the Agilex™ 5 FPGA E-Series devices with a speed grade -6s or -6x? - Why does the Configuration Clock IP generate an SDC file with incorrect constraints for the Agilex™ 5 FPGA E-Series devices with a speed grade -6s or -6x? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, you might see the Configuration Clock IP satiating incorrectly that the configuration clock of Agilex™ 5 FPGA E-Series devices with a speed grade -6s or -6x to run at 250 MHz. The configuration clock runs at 200 MHz for these devices. Additionally, the sdc files generated for the Configuration Clock Intel FPGA IP incorrectly constrain the configuration clock “ altera_int_osc_clk ” to the wrong frequency. Resolution To avoid this problem, change the configuration the clock constraint as shown below: if {[get_collection_size [get_clocks altera_int_osc_clk -nowarn]] == 0} { create_clock -name altera_int_osc_clk -period 5.000 [get_nodes {*|intosc|oscillator_dut~oscillator_clock.reg}] } This problem is fixed in Quartus® Prime Pro Edition Software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 22020299153 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.2 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']