Backplane Ethernet 10GBASE-KR PHY FPGA IP - The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate the hard standard physical coding sublayer (PCS), the higher… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate both the hard standard physical coding sublayer (PCS), the higher performance hard 10G PCS, and the hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE 802.3ap-2007 standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multichannel designs by instantiating more than one instance of the core. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Backplane Ethernet 10GBASE-KR PHY FPGA IP Key Features Integrated 1000BASE-KX / 10GBASE-KR (1G/10Gb) Backplane Ethernet PCS and PMA Offering Brief No No No Yes Encrypted Verilog Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes Offering Brief Production a1JUi0000049UUqMAM What's Included Encrypted Verilog source code Ordering Information IP-10GBASEKRPHY (Stratix 10); IP-10GMRPHY (Arria 10) Digikey Mouser a1JUi0000049UUqMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T18:42:48.000+0000 The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate the hard standard physical coding sublayer (PCS), the higher performance hard 10G PCS, and the hard physical medium attachment (PMA) for a single Backplane Ethernet channel. Altera Solutions