Why can't some DDR3 HMC control registers be read or written by the CSR interface? - Why can't some DDR3 HMC control registers be read or written by the CSR interface? Description There is an issue while using the CSR interface to read and write DDR3 hard memory controller (HMC) control registers in both simulation and lab for the Cyclone® V and Arria® V devices. Some DDR3 HMC control registers can't be read back or written in. The Controller Register map in Table 5-18 in the external memory interface handbook is for the DDR3 soft memory controller, and not for the DDR3 HMC. Resolution This issue has been fixed in the current release of the external memory interface handbook. Custom Fields values: ['novalue'] Troubleshooting 2205967785 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']