Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings - Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings Description You might see this error in the Supported-Logic Generation step when the F-tile PMA/FEC Direct PHY Intel® FPGA IP set PMA Interface Width=10 and F-tile Interface FIFO=Phase Compensation mode. According to Table 24. PMA Direct Mode Support in F-tile Architecture and PMA and FEC Direct PHY IP User Guide, when PMA modulation=NRZ, PMA mode=FGT, Clocking Mode=PMA Clocking, Double Width/Single Width=SW, PMA Interface Width=10 and F-tile Interface FIFO should be Register mode. Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, there is no error message generated when you set like this in the F-Tile PMA/FEC Direct PHY Intel FPGA IP. Resolution This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 15012169028 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 21.4 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']