Do user I/O pins drive high during transition from input tri-state with weak pull-up to LVDS I/O standard in initialization stage in Stratix® V devices? - Do user I/O pins drive high during transition from input tri-state with weak pull-up to LVDS I/O standard in initialization stage in Stratix® V devices? Description Yes. Due to the specifications of the user I/O element, user I/O pins drive high during the transition from input tri-state with weak pull-up to LVDS I/O standard in the initialization stage in Stratix® V devices. Resolution So the state of the user I/O pins designed as LVDS I/O standard changes from weak pull-up to VCCIO, high state driven from VCCIO, to LVDS I/O standard in the initialization stage. Custom Fields values: ['novalue'] Troubleshooting 1507899627 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']