Why is the Slot Clock Configuration bit setting of the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express is always 0 regardless of the setting in the IP Catalog? - Why is the Slot Clock Configuration bit setting of the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express is always 0 regardless of the setting in the IP Catalog? Description Due to a problem with the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express in Intel® Quartus® Prime Pro Edition Software version 19.4, the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register is always set to 0. This problem can be seen in both simulation and hardware. Resolution There is no workaround. Custom Fields values: ['novalue'] Troubleshooting 1507878462 True ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.4 ['Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']