Incorrect Port Direction for SerialLite II IP Core Targeting Arria® V, Cyclone® V, and Stratix® V Devices - Incorrect Port Direction for SerialLite II IP Core Targeting Arria® V, Cyclone® V, and Stratix® V Devices Description The SerialLite II IP core incorrectly sets the direction for the err_rr_8berrdet port as the output port. This issue affects Arria® V, Cyclone® V, and Stratix® V devices. Resolution To work around this issue, change the direction of the err_rr_8berrdet port to input and connect the port to the r x_errdetect output port of the Custom PHY transceiver. This problem has been fixed in version 18.1 of the SerialLite II IP core. Custom Fields values: ['novalue'] Troubleshooting 2205700727 True ['SerialLite II v18.1'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 18.1 15.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']