Why does my NCSim Gen3 PIPE simulation fail to compile for Intel® Arria® 10 FPGAs? - Why does my NCSim Gen3 PIPE simulation fail to compile for Intel® Arria® 10 FPGAs? Description When using Quartus® II software release 14.0a10, the Hard IP for PCI Express does not compile under Cadence NCSim in PIPE mode. This problem is due to a timescale directive discrepancy with the simulator. Resolution Use serial mode simulation as described in the user guide. This problem will be fixed in a future release of the Quartus development software. Custom Fields values: ['novalue'] Troubleshooting - False ['PCI Express', 'Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0a10 ['Arria® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']