Why do the signals (nodes) in the Signal Tap Logic Analyzer disappear? - Why do the signals (nodes) in the Signal Tap Logic Analyzer disappear? Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 or earlier, the signals (nodes) initially displayed in the Signal Tap Logic Analyzer might disappear after the trigger occurs. This is because the checkbox in the "Hierarchy Display" GUI window becomes unchecked, causing the signals to be hidden. This problem only occurs when running on Windows* OS. Resolution To work around the problem, manually enable the checkbox in the "Hierarchy Display" GUI window. This problem is fixed beginning with the Quartus® Prime Standard Edition Software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 15014572807 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 24.1 23.1 ['Arria® II FPGAs', 'Arria® V GZ FPGA', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 LP FPGA', 'MAX® 10 10 FPGAs', 'MAX® II CPLDs', 'MAX® V CPLDs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']