Why does the the Avalon®-MM Intel® Stratix® 10 Hard IP for PCI* Express IP’s dynamically generated example design with Avalon®-MM does not provide int_req_i as input pin? - Why does the the Avalon®-MM Intel® Stratix® 10 Hard IP for PCI* Express IP’s dynamically generated example design with Avalon®-MM does not provide int_req_i as input pin? Description Due to a problem with the Intel®Quartus® Prime Pro version 18.0 and 18.1, the Intel® Stratix® 10 Avalon®-MM PCI Express* Hard IP Example Design generates RTL with int_req_i set to 0 instead of set as an input pin in the top level file, pcie_example_design_DUT.v int_req_i is a legacy interrupt input pin that is available when “Enable MSI/MSI-X conduit interfaces” is selected. This issue only exist when Avalon®-MM address width is set to 64bit. Resolution To workaround this problem in the Quartus® Prime Pro version 18.0 and 18.1 follow the steps below: Make the following changes to the top level file, pcie_example_design_DUT.v input wire intx_req_i, //specify as input port dut ( .intx_req_i (intx_req_i), //replace 1’b0 with the intx_req_i ); This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro version 19.1 Custom Fields values: ['novalue'] Troubleshooting 00400046 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.0 ['Programmable Logic Devices', 'Stratix® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']