Why do I get the error "Unknown uid = xhip_block_1_1" when executing the a10_disableiei.tcl script to disable electrical idle inference for the Intel® Arria® 10 and Intel® Cyclone® 10 GX PCI-SIG Compliance Base Board (CBB) design? - Why do I get the error "Unknown uid = xhip_block_1_1" when executing the a10_disableiei.tcl script to disable electrical idle inference for the Intel® Arria® 10 and Intel® Cyclone® 10 GX PCI-SIG Compliance Base Board (CBB) design? Description The a10_disableiei.tcl script disables electrical idle inference for all 4 PCIe* Hard IPs of the Intel® Arria® 10. Therefore, for Intel® Arria® 10 and Intel® Cyclone® 10 GX that have less than 4 PCIe* Hard IPs, executing the script will return this error. Internal Error: Sub-system: ASM2, File: /quartus/comp/asm2/asm2_state.cpp, Line: 1469 Unknown uid = xhip_block_1_1 Resolution To work around this problem, comment out the unavailable PCIe* Hard IPs in the a10_disableiei.tcl script. For example, the 10AX115N1F40I1LP device uses only 2 PCIe* Hard IPs, not 4. Therefore, the 2 unavailable Hard IPs, xhip_block_1_1 and xhip_block_3_1, should be commented out. xhip_block_1_0 = Bottom Left Location xhip_block_1_1 = Top Left Location xhip_block_3_0 = Bottom Right Location xhip_block_3_1 = Top Right Location Custom Fields values: ['novalue'] Troubleshooting 1507165133 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']