Why does the Serial Lite III Streaming FPGA IP design VHDL simulation fail using QuestaSim and Questa*- FPGA Edition Software? - Why does the Serial Lite III Streaming FPGA IP design VHDL simulation fail using QuestaSim and Questa*- FPGA Edition Software? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, you might observe VHDL simulation failures for the Serial Lite III Streaming IP design with Standard Clocking Mode for the Stratix® 10 L/H-tile devices when using the latest version of QuestaSim and Questa*- FPGA Edition Software. Resolution To avoid this simulation failure, you can use the previous Questa Simulator version 2022.1. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16019267128 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.1 ['Stratix® 10 AX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']