Is the conf_reset input in the Intel Configuration Reset Release Endpoint to Debug Logic IP asynchronous? - Is the conf_reset input in the Intel Configuration Reset Release Endpoint to Debug Logic IP asynchronous? Description Yes, the conf_reset input in the Intel® Configuration Reset Release Endpoint to Debug Logic IP is an asynchronous signal. Resolution A future release of the Intel® Quartus® Prime Pro Edition Software User Guide: Partial Reconfiguration will be updated with this information. Custom Fields values: ['novalue'] Troubleshooting 18027915905 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.2 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']