How do I perform IBIS simulation when a VREF pin is used as general purpose regular I/O pin? - How do I perform IBIS simulation when a VREF pin is used as general purpose regular I/O pin? Description The pin capacitance is higher on VREF pins than general purpose I/O pins. The IBIS models do not contain the additional pin capacitance for the VREF pins when used as regular I/O pins. You should add an input capacitor to your IBIS simulation to account for the additional capacitance. Refer to the respective device datasheet for the VREF pin capacitance value for the device you are targeting. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA'] ['novalue'] ['novalue'] ['novalue']