RapidIO II Simulation testbench failure when parameter "Enable Transceiver control and status register" is enabled. - RapidIO II Simulation testbench failure when parameter "Enable Transceiver control and status register" is enabled. Description For Arria® 10 and Stratix® 10 families. When RapidIO II IP Core is generated with the optional parameter " Enable transceiver control and status register " enabled, the provided simulation testbench will fail. The failing behavior is that the transceiver does not exit from reset, and rx_is_lockedtodata does not assert. Resolution Advice is to run the simulation without enabling the parameter " Enable transceiver control and status register " if affected. This problem has been fixed starting in Quartus® Prime software version 17.0. Custom Fields values: ['novalue'] Troubleshooting FB: 440420; True ['RapidIO II (IDLE2 up to 6.25 Gbaud) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']