Why does the Stratix® 10 FPGA Avalon® memory mapped Interface for PCIe with DMA design example fail the link test and the DMA test when using the default setting BAR0? - Why does the Stratix® 10 FPGA Avalon® memory mapped Interface for PCIe with DMA design example fail the link test and the DMA test when using the default setting BAR0? Description When the internal DMA Descriptor Controller is enabled, the BAR0 Avalon® memory mapped host interface is not available for general-purpose usage. The DMA Descriptor Controller uses this BAR0 interface through which the host CPU programs in the descriptor table. The intel_fpga_pcie_link_test user application selects BAR0 as the default setting when it's initially executed. If you forget to change the setting to BAR2 , which is where the on-chip memory is attached, then both the link test and the DMA test will fail. Resolution You must change the default setting to BAR2 before executing the link test and the DMA test. See the following execution transcript of the intel_fpga_pcie_link_test user application for steps on how to change the setting to BAR2 . ~$ sudo ./intel_fpga_pcie_link_test ********************************************************* FPGA PCIe Link Test Version 2.0 0: Automatically select a device 1: Manually select a device ********************************************************* > 0 Opened a handle to BAR 0 of a device with BDF 0x1300 ********************************************************* 0: Link test - 100 writes and reads 1: Write memory space 2: Read memory space 3: Write configuration space 4: Read configuration space 5: Change BAR 6: Change device 7: Enable SRIOV 8: Do a link test for every enabled virtual function belonging to the current device 9: Perform DMA 10: Quit program ********************************************************* > 5 Changing BAR... Enter BAR number (-1 for none): > 2 Successfully changed BAR! Custom Fields values: ['novalue'] Troubleshooting 2206974976 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-MM Stratix® 10 Hard IP+ for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']