Incremental Block-Based Compilation in the Altera® Quartus® Prime Pro Software: Timing Closure & Tips - 22 Minutes This training is part 3 of 3. Designing, organizing, and optimizing a large FPGA design can be difficult and time consuming. Every change made to fix a problem or to help close timing requires the design to be completely recompiled. Not only can this take a long time, but the placement and routing of untouched parts of the design can be affected. In this training, you will learn about incremental block-based compilation, the ability to partition your design and choose which parts should be reused in subsequent compilations. This feature will help you preserve performance and close timing faster. This final part of the training provides some general tips & techniques as well as a methodology for using the feature to close timing. Course Objectives At course completion, you will be able to: Set up and perform incremental block-based compilation through design partition creation in the Altera® Quartus® Prime Pro Edition software Understand the different design methodologies (top-down, bottom-up) for implementing a block-based design Preserve compiled design partitions by reusing previous compilation results in a single project Skills Required Basic knowledge of the Altera® Quartus Prime software knowledge of creating FPGA designs in a hardware description language (Verilog or VHDL) If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OIBBC102. FPGA_OIBBC102. <p>Incremental Block-Based Compilation in the Altera Quartus Prime Pro Software: Timing Closure & Tips</p>