Why signal fixedclk_locked is not in the port list? - Why signal fixedclk_locked is not in the port list?
Description In the Stratix ® V Hard IP PCIe core v12.0, the fixedclk is driven by Serdes reference clock input ref_clk directly, so the signal fixedclk_locked signal is removed from the port list. Resolution
Custom Fields values:
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Troubleshooting
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False
['PCI Express']
['FPGA Dev Tools Quartus II Software']
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11.0
['Stratix® V GX FPGA']
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['novalue']
['novalue'] - 2021-08-25
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