Why does the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled? - Why does the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example may fail timing closure when configured at 25Gbps and Interlaken Look-aside mode is enabled. Resolution To work around this problem in the Intel® Quartus® Prime Pro Software version 22.1 and earlier, launch the Design Space Explorer II in the Intel® Quartus® Prime Pro Software and perform seed sweeps. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 1508954783 1508277122 False ['Interlaken (2nd Generation) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['Stratix® 10 GX FPGA Signal Integrity Dev Kit', 'Stratix® 10 TX FPGA Signal Integrity Dev Kit']